1. Field of the Invention
The invention generally relates to a buffer module and a data buffering method, and more particularly, to an elastic buffer module of a transmission interface and a data buffering method thereof.
2. Description of Related Art
High-speed transmission interfaces, such as peripheral component interconnect (PCI) express interfaces and universal serial bus (USB) 3.0 interfaces, have been broadly applied for transmitting data among computers and high-performance chips. Such a high-speed transmission interface is usually composed of two low-voltage differential pairs. One of the differential pairs is configured to transmit data, while the other differential pair is configured to receive data. The end close to the processor is usually referred to as an upstream port (UP), while the end away from the processor is usually referred to as a downstream port (DP). The transmitting side of the UP is connected with the receiving side of the DP, and the receiving side of the UP is connected with the transmitting side of the DP.
In order to increase the transmission rate of a conventional parallel interface, a high-speed transmission interface usually adopts the low-voltage differential transmission technique, in which noise interference is eliminated through the differential characteristic, and the voltage level is reduced to increase the transmission rate to the level of gigabyte per second (Gbps)). In addition, a high-speed transmission interface usually has a logic circuit for converting analog signals of the high-speed transmission interface into digital signals compliant with protocols of other layers. Herein the logic circuit at the receiving side needs to deal with the issue of asynchronous timing between the receiving side and the transmitting side of the other port. The asynchronous timing is produced due to the different circuit systems of UP and RX, the spread spectrum clocking (SSC), and the lack of a common clock. A complementary symbol is usually defined as an auxiliary data and used to increase the elasticity in the adjustment of transmission rates. The auxiliary data does not carry any information. When the receiving side is slower than the transmitting side and accordingly the receiving side cannot process data received from the transmitting side in time, the circuit at the receiving side directly removes the auxiliary data from the original data sequence to avoid overflow. Contrarily, when the receiving side is faster than the transmitting side and accordingly the transmitting side cannot provide data to the receiving side in time, the circuit at the receiving side adds the auxiliary data into the original data sequence to avoid underflow.
Conventionally, to resolve the problem of speed difference between a transmitting side and a receiving side, an elastic buffer is usually adopted, and a buffering management circuit is disposed in the elastic buffer to prevent the occurrence of underflow or overflow. However, a conventional data buffering technique usually requires a large buffering space and tolerates a very small speed difference between the transmitting side and the receiving side.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.